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Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. But SPEF does not include inductances. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation. SPEF is most popular specification for parasitic exchange between different tools of EDA domain during any phase of design. The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System . Latest version of SPEF is part of 1481-2009 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) . SPEF is extracted after routing in Place and route stage. This helps in accurate calculation of IR-drop analysis and other analysis after routing. This file contains the R and C parameters depending on the placement of our tile/block and the routing among the placed cells.. == SPEF syntax == SPEF (Standard Parasitic Exchange Format) is documented in chapter 9 of IEEE 1481-1999. Several methods of describing parasitics are documented, but we are discussing only few important one. General Syntax A typical SPEF file will have 4 main sections – a header section, – a name map section, – a top level port section and – the main parasitic description section. Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP and *D_NET. Comments start anywhere on a line with // and run to the end of the line. Each line in a block of comments must start with //. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Standard Parasitic Exchange Format」の詳細全文を読む スポンサード リンク
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